EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 20

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
PS006614-1208
Pin
No.
35
36
37
38
39
40
41
Symbol
ADDR21 Address Bus
ADDR22 Address Bus
ADDR23 Address Bus
V
GND
DATA0
DATA1
DD
Function
Power Supply
Ground
Data Bus
Data Bus
Signal Direction
Input/Output
Input/Output
Input/Output
Bidirectional,
tristate
Bidirectional,
tristate
Description
The ADDR21 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR22 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR23 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
Power Supply
Ground
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
Product Specification
Architectural Overview
10