EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 60

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chip Selects and Wait States
Memory and I/O Chip Selects
Memory Chip Select Operation
PS006614-1208
The eZ80190 device generates four Chip Selects for external devices. Each Chip Select
may be programmed to access either memory space or I/O space. The Memory Chip
Selects can be individually programmed on a 64 KB boundary. The I/O Chip Selects can
each choose a 16-byte section of I/O space. In addition, each Chip Select may be pro-
grammed for up to 7 WAIT states.
Each of the four available Chip Selects can be enabled for either the memory address
space or the I/O address space, but not both. To select the memory address space for a par-
ticular Chip Select, CS_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address
space for a particular Chip Select, CS_IO must be set to 1. After RESET, the default is for
all Chip Selects to be configured for the memory address space. For either the memory
address space or the I/O address space, the individual Chip Selects must be enabled by set-
ting CS_EN (CSx_CTL[3]) to 1.
Each of the four Memory Chip Selects features three control registers. To enable a particu-
lar Memory Chip Select, the following conditions must be met:
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If all of the foregoing conditions are met to generate a Memory Chip Select, then the fol-
lowing actions occur:
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The Chip Select is enabled by setting CS_EN to 1
The Chip Select is configured for memory by clearing CS_IO to 0
The address is in the associated Chip Select range:
CSx_LBR[7:0] ≤ ADDR[23:16] ≤ CSx_UBR[7:0]
No higher priority (lower number) Chip Select meets the above three conditions
No on-chip RAM is configured for the same address space, because on-chip RAM is
prioritized higher than all Memory Chip Selects
A memory access instruction must be executing
A Chip Select—CS0, CS1, CS2, or CS3—is activated (driven Low)
The MREQ signal is activated (driven Low)
Chip Selects and Wait States
Product Specification
eZ80190
50