EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 105

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Synchronization
PS006614-1208
Data Output by Transmitter
Data Output by Receiver
SCL Signal From Master
All masters generate their own clocks on the SCL line to transfer messages on the I
Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I
to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant
devices to start counting from their Low period. When a device clock goes Low, it holds
the SCL line in that state until the clock High state is reached. See
The Low-to-High transition of this clock, however, may not change the state of the SCL
line if another clock still exists within its Low period. The SCL line is held Low by the
device with the longest Low period. Devices with shorter Low periods enter a High WAIT
state during this time.
When all devices complete counting off their Low periods, the clock line goes High. There
is no difference between the device clocks and the state of the SCL line; therefore, all of
the devices begin counting their High periods. The first device to complete its High period
again pulls the SCL line Low. In this way, a synchronized SCL clock is generated with its
Low period determined by the device with the longest clock Low period, and its High
period determined by the device with the shortest clock High period.
Start Condition
S
Figure 19. I
1
2
C Acknowledge
2
Clock Pulse for Acknowledge
8
9
Product Specification
Figure 20
I2C Serial I/O Interface
2
on page 96.
C interfaces
2
C bus.
95