EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 102

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
I
PS006614-1208
2
2
C General Characteristics
C Serial I/O Interface
Clocking Overview
Bus Arbitration Overview
The I
modes:
1. MASTER TRANSMIT
2. MASTER RECEIVE
3. SLAVE TRANSMIT
4. SLAVE RECEIVE
The I
and SCL are bidirectional lines, connected to a positive supply voltage via an external
pull-up resistor. When the bus is free, both lines are High. The output stages of devices
connected to the bus must be configured as open-drain outputs. Data on the I
transferred at a rate of up to 100 kbps in STANDARD mode, or up to 400 kbps in FAST
mode. One clock pulse is generated for each data bit transferred.
If another device on the I
TER mode, the I
clock is determined by the device that generates the shortest High clock period. The Low
period of the clock is determined by the device that generates the longest Low clock
period.
A slave may stretch the Low period of the clock to slow down the bus master. The Low
period can also be stretched for handshaking purposes. For both circumstances, this Low
period can be stretched after each bit transfer or each byte transfer. The I
clock after each byte transfer until the IFLG bit in the I2Cx_CTL register is cleared.
In MASTER mode, the I
a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a NACK bit, the I
returns to the IDLE state. If arbitration is lost during the transmission of an address, the
I
call address.
2
C switches to SLAVE mode so that it can recognize its own slave address or the general
2
2
C interface consists of the Serial Clock (SCL) and the Serial Data (SDA). Both SDA
C serial I/O bus is a two-wire communication interface that can operate in four
2
C synchronizes its clock to the I
2
2
C checks that each transmitted logic 1 appears on the I
C bus drives the clock line when the I
2
C bus clock. The High period of the
2
Product Specification
C is operating in MAS-
I2C Serial I/O Interface
2
C stretches the
2
C bus can be
2
C bus as
2
C
92