EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 151

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DMA Transfer Modes
PS006614-1208
BUSREQ
BUSACK
DMA
write
DMA
read
CLK
From Source Address
There are two modes of operation for the DMA channels. The DMA can transfer data in
BURST mode or CYCLE-STEAL mode. The data transfer mode is controlled by the
BURST bit in the DMA Control registers (DMAx_CTL[4]).
In BURST mode, the DMA controller takes control of the bus within the eZ80190 device
for the entire time period required to complete the data transfer. The CPU is idled while
the DMA controller completes its BURST mode data transfer.
The default operation for the DMA controller is CYCLE-STEAL mode in which the DMA
controller requests and then gains access to the bus for the transfer of only one byte at a
time. After the transfer of each byte, the DMA returns control of the bus back to the CPU.
The DMA then waits for the CPU to complete 8 clock cycles before again requesting con-
trol of the bus. As a result, other activities can proceed while the DMA is transferring data
in the background. CYCLE-STEAL mode slows down the processing of the main pro-
gram task of the CPU. See
DMA Reads Data
Current Instruction
To Destination Address
DMA Writes Data
eZ80
DMA Initiates
Bus Request
®
Figure 25. DMA CYCLE-STEAL Timing
eZ80
Figure
Bus to DMA
®
Release
25.
In Cycle-Steal Mode, DMA will Request
1
DMA Returns
Bus to eZ80
the Bus Again on the 8th Clock Cycle
Following Return of the Bus
2
3
®
4
New Bus Request
DMA Initiates
eZ80
Direct Memory Access Controller
Return of the Bus
5
®
Product Specification
Acknowledge
6
7
8
eZ80190
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