EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 98

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SPI Flags
PS006614-1208
Mode Fault
Write Collision
written to the shift register, eight clocks are generated to shift the eight bits of data in both
directions. The SCK signal then enters the IDLE state.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin, and the slave is synchronized to the master. Data from the master is
received serially from the slave MOSI signal and loads the 8-bit shift register. After the 8-
bit shift register is loaded, its data is parallel transferred to the read buffer. During a write
cycle data is written into the shift register, then the slave waits for the SPI master to initiate
a data transfer, supply a clock signal, and shift the data out on the slave's MISO signal.
If the CPHA bit in the SPIx_CTL register is 0, a transfer begins when SS pin signal goes
Low and the transfer ends when SS goes High after eight clock cycles on SCK. When the
CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low
and the transfer ends when the SPIF flag gets set.
The Mode Fault flag (SPIx_SR[4] = MODF) indicates that there may be a multimaster
conflict for system control. The MODF bit is normally cleared to 0. It is only set to 1 when
the master device’s SS pin is pulled Low. When a mode fault is detected, the following
occurs:
1. The MODF flag (SPIx_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPIx_CTL[5]) to 0.
3. The MASTER_EN bit (SPIx_CTL[4]) is cleared to 0, forcing the device into SLAVE
4. If enabled (IRQ_EN = SPIx_CTL[7] = 1), an SPI interrupt is generated.
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault flag is cleared.
The WRITE COLLISION flag (SPIx_SR[5] = WCOL) is set to 1 when an attempt is made
to write to the SPI Transmit Shift register (SPIx_TSR) while data is being transferred.
Clearing the WCOL bit is performed by reading SPIx_SR with the WCOL bit set.
mode.
Product Specification
Serial Peripheral Interface
eZ80190
88