EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 82

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART Registers
PS006614-1208
Data Transfers
Poll Mode Transfers
Transmit—
immediately expected in response to this interrupt. The application reads the UARTx_IIR
register and determines that the interrupt occurs because of an empty UARTx_THR regis-
ter. When the application determines this occurrence, the application writes the transmit
data bytes to the UARTx_THR register. The number of bytes that the application writes
depends on whether or not the FIFO is enabled. If the FIFO is enabled, the application can
write 16 bytes at one time. If the FIFO is not enabled, the application can Write Only one
byte at a time. As a result of the first write, the interrupt is deactivated. The processor then
waits for the next interrupt. When the interrupt is raised by the UART module, the proces-
sor repeats the same process until it exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by writing to
UARTx_MCTL register and reading from the UARTx_MSR register before starting the
above process.
Receive—
RXD input signal. When an interrupt is raised by the UART module, the application reads
the UARTx_IIR register and determines the cause of the interrupt. If the cause is a line sta-
tus interrupt, the application reads the UARTx_LSR register, reads the data byte, then dis-
cards the byte or takes other action. If the interrupt is caused by a RECEIVE DATA
READY condition, the application alternately reads the UARTx_LSR and UARTx_RBR
registers and removes all received data bytes. It reads the UARTx_LSR register before
reading the UARTx_RBR register to determine if there is a NO ERROR condition in the
received data.
To control and check modem status, the application sets up the modem by writing to the
UARTx_MCTL register and reading the UARTx_MSR register before starting the above
process.
When interrupts are disabled, all data transfers are referred to as poll mode transfers. In
poll mode transfers, the application must continually poll the UARTx_LSR register to
transmit or receive data without enabling the interrupts. This condition is also true for the
UARTx_MSR register. If the interrupts are not enabled, the data in the UARTx_IIR regis-
ter cannot be used to determine the cause of an interrupt.
After a system reset, all UART registers are set to their default values. Any writes to
unused registers or register bits are ignored. READs return a value of 0. For compatibility
with future versions of this part, unused bits within a register should always be written
The receiver is always enabled and continually checks for the start bit on the
To transmit data, the application enables the transmit interrupt. An interrupt is
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80190
72