EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 90

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Bit
Position
7
ERR
6
TEMT
5
THRE
4
BI
3
FE
2
PE
Value
0
1
0
1
0
1
0
1
0
1
0
1
Description
This bit is always 0 when operating with the FIFO disabled.
With the FIFO enabled, this bit is reset when the UARTx_LSR
register is read and there are no more bytes with an error
status in the FIFO.
An error is detected in the FIFO. There is at least 1 parity,
framing, or Break Indication (BI) error in the FIFO.
The Transmit Holding Register FIFO is not empty, the Transmit
Shift Register is not empty, or the transmitter is not idle.
The Transmit Holding Register FIFO and the Transmit Shift
Register are empty; the transmitter is idle. This bit cannot be
set to 1 during the Break Indication (BI). This bit is set to 1 only
after the BREAK command is removed.
The Transmit Holding Register FIFO is not empty.
The Transmit Holding Register FIFO bit cannot be set to 1
during the Break Indication (BI). This bit is set to 1 only after
the BREAK command is removed.
The receiver does not detect a Break Indication. This bit is
reset to 0 when the UARTx_LSR register is read.
The receiver detects a Break Indication on the receive input
line. This bit is set to 1 if the duration of the Break Indication on
the receive data is longer than one character transmission
time, the time depends on the programming of the
register. In the case of a FIFO, only one null character is
loaded into the receive FIFO with the framing error. The
framing error is revealed to the eZ80
string of data is read from the receive FIFO.
No framing error is detected for the character at the top of the
FIFO. This bit is reset to 0 when the UARTx_LSR register is
read.
A framing error is detected for the character at the top of the
FIFO. This bit is set to 1 when the stop bit following the data/
parity bit is logic 0.
The received character at the top of the FIFO does not produce
a parity error. This bit is reset to 0 when the UARTx_LSR
register is read.
The received character at the top of the FIFO contains a parity
error.
Universal Asynchronous Receiver/Transmitter
®
whenever this particular
Product Specification
UARTx_LSR
eZ80190
80