EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 27

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
PS006614-1208
Pin
No.
74
75
76
Symbol
PC7
RI1
TEST
PD0
MISO0
SCL0
TxD0
Function
GPIO Port C
Ring Indicator Input, Active Low
Test
GPIO Port D
Master In
Slave Out
I
Clock
Transmit Data Output
2
C Serial
Signal Direction
Input/Output
Input, Active High
Input/Output
Input/Output
Input/Output
Description
The PC7 pin can be used for GPIO. It can be
individually programmed as an input or output
and can also be used individually as an interrupt
input. Each Port C pin, when programmed as an
output, can be selected to be an open-drain or
open-source output. Port C is multiplexed with
one channel of the UZI interface.
The RI1 pin carries the modem status signal to
the UART. This signal is multiplexed with PC7.
The TEST pin places the chip in TEST mode. It is
used only for factory testing. This signal should
be tied Low for normal operation.
The PD0 pin can be used for GPIO. It can be
individually programmed as an input or output
and can also be used individually as an interrupt
input. Each Port D pin, when programmed as an
output, can be selected to be an open-drain or
open-source output. Port D is multiplexed with
one channel of the UZI interface.
The MISO line is configured as an input when the
eZ80190 device is an SPI master device and as
an output when eZ80190 device is an SPI slave
device. This signal is multiplexed with PD0.
This pin is used to receive and transmit the I
clock. This signal is multiplexed with PD0.
The TxD0 pin is used by the UART to transmit
asynchronous serial data. This signal is
multiplexed with PD0.
Product Specification
Architectural Overview
2
C
17