EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 120

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Note:
I
2
C Clock Control Register
Table 54. I
If an illegal condition occurs on the I
00h
IFLG bit cleared. The I
ted on the I
The STP and STA bits may be simultaneously set to 1 to recover from the bus error. The
I
The I2Cx_CCR register, listed in
least significant byte (LSB)s control the frequency at which the I
frequency of the I
Write Only I2Cx_CCR registers share the same I/O addresses as the Read Only I2Cx_SR
registers.
Code
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
B0h
B8h
C0h
C8h
D0h
D8h
F8h
2
C then sends a START.
). To recover from this state, the STP bit in the I2Cx_CTL register must be set and the
2
2
Status
Arbitration lost in address as master, slave address + write bit received, ACK
transmitted
General Call address received, ACK transmitted
Arbitration lost in address as master, General Call address received, ACK
transmitted
Data byte received after slave address received, ACK transmitted
Data byte received after slave address received, NACK transmitted
Data byte received after General Call received, ACK transmitted
Data byte received after General Call received, NACK transmitted
STOP or repeated START condition received in SLAVE mode
Slave address + read bit received, ACK transmitted
Arbitration lost in address as master, slave address + read bit received, ACK
transmitted
Data byte transmitted in SLAVE mode, ACK received
Data byte transmitted in SLAVE mode, ACK not received
Last byte transmitted in SLAVE mode, ACK received
Second Address byte + write bit transmitted, ACK received
Second Address byte + write bit transmitted, ACK not received
No relevant status information, IFLG = 0
C Status Codes (Continued)
C bus.
2
C clock line (SCL) when the I
2
C then returns to the IDLE state. No STOP condition is transmit-
Table 55
2
C bus, the bus error state is entered (status code
on page 111, is a Write Only register. The seven
2
C is operating in MASTER mode. The
2
Product Specification
C bus is sampled and the
I2C Serial I/O Interface
110