AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1041

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.7.41
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPSWS3 and WPHWS3 bits are cleared in
1029.
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 20 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
32117C–AVR-08/11
– By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using the PWM internal clock (CCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM internal clock (CCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
31
23
15
7
-
256, 512, or 1024). The resulting period formula will be:
respectively:
256, 512, or 1024). The resulting period formula will be:
(
--------------------------------------------
(
------------------------------------------------------- -
X CPRDUPD
CRPDUPD DIVA
Channel Period Update Register
×
CCK
CCK
×
30
22
14
6
-
CPRDUPD
Write-only
0x210 + [ch_num * 0x20]
-
)
)
or
(
------------------------------------------------------- -
CRPDUPD DIVB
29
21
13
5
-
CCK
×
)
28
20
12
4
-
CPRDUPD
CPRDUPD
CPRDUPD
27
19
11
3
-
26
18
10
2
-
”Write Protect Status Register” on page
25
17
9
1
-
AT32UC3C
24
16
8
0
-
1041