AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 165

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 10-4. Window Mode WDT Timing Diagram
Figure 10-5. Window Mode WDT Timing Diagram, clearing within T
32117C–AVR-08/11
C L R .W D T C L R
W a tc h d o g re s e t
C L R .W D T C L R
W a tch d o g re s e t
t= t
t= t
W rite o n e to
W rite o n e to
0
0
The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT
timeout period
where T
bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the
code will start executing form the boot vector, see
will be cleared.
Writing a one to the CLR.WDTCLR bit within the T
counter starts counting from zero (t=t
If the value in the CTRL Register is changed, the WDT counter will be cleared without a watch-
dog reset, regardless of if the value in the WDT counter and the TBAN value.
If the WDT counter reaches T
and the code will start executing form the boot vector.
T
T
tb a n
tb a n
T
timeout
tban
sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR
= T
tban
+ T
psel
= (2
timeout
(TBAN+1)
, the counter will be cleared, the device will receive a reset
0
), entering T
+ 2
(PSEL+1)
tban
, resulting in watchdog reset.
T
T
p s e l
) / f
p s e l
tban
psel
Figure 10-5 on page
clk_cnt
, see
period will clear the WDT counter and the
Figure 10-4 on page
165. The WDT counter
AT32UC3C
T im e o u t
T im e o u t
165.
165