AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 805

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.3
30.6.4
32117C–AVR-08/11
Master, Controller, and Slave Modes
I
2
S Reception and Transmission Sequence
The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), when-
ever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values
written to THR should correspond to the samples from the left and right audio channels, or from
channels 0 to MR.NBCHAN in TDM mode, for the successive frames.
The Receive Ready and Transmit Ready bits can be polled by reading the Status Register.
The IISC processor load can be reduced by enabling interrupt-driven operation. The RXRDY
and/or TXRDY interrupt requests can be enabled by writing a one to the corresponding bit in the
Interrupt Enable Register (IER). The interrupt service routine associated to the IISC interrupt
request will then be executed whenever the Receive Ready or the Transmit Ready status bit is
set.
In Master and Controller modes, the IISC provides the Master Clock, the Serial Clock and the
Word Select. IMCK, ISCK, and IWS pins are outputs.
In Controller mode, the IISC Receiver and Transmitter are disabled. Only the clocks are enabled
and used by an external receiver and/or transmitter.
In Slave mode, the IISC receives the Serial Clock and the Word Select from an external master.
ISCK and IWS pins are inputs.
The mode is selected by writing the MODE field of the Mode Register (MR). Since the MODE
field changes the direction of the IWS and ISCK pins, the Mode Register should only be written
when the IISC is stopped, in order to avoid unwanted glitches on the IWS and ISCK pins.
As specified in the I
MSB transmitted first, starting one clock period after the transition on the Word Select line.
Figure 30-2. I
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the
Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left
channel and a high level for the right channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing
the MR.DATALENGTH field.
If the time slot allows for more data bits than written in the MR.DATALENGTH field, zeroes are
appended to the transmitted data word or extra received bits are discarded. If the time slot
allows for less data bits than written, the extra bits to be transmitted are not sent or the missing
bits are set to zero in the received data word.
Serial Clock ISCK
Word Select IWS
Data ISDI/ISDO
2
S Reception and Transmission Sequence
2
S protocol, data bits are left-adjusted in the Word Select time slot, with the
MSB
Left Channel
LSB
AT32UC3C
MSB
Right Channel
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