AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 516

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.7.7
Name:
Access Type:
Offset:
Reset Value:
This register, when read, returns details of the status of a receive. Once read, individual bits may be cleared by writing a
one to them. It is not possible to write a bit to one by writing to the register.
• OVR: Receive Overrun
• REC: Frame Received
• BNA: Buffer Not Available
32117C–AVR-08/11
31
23
15
7
-
-
-
-
This bit is set when the DMA interface is unable to store the receive frame to memory, either because the bus was not granted in
time or because a bus error was returned. The buffer is recovered if this happens.
Write a one to clear this bit.
0: No receive overrun detected.
1: Receive overrun detected.
This bit is set when one or more frames have been received and placed in memory.
Write a one to clear this bit.
0: No frame received.
1: Frame received.
The DMA reads the pointer each time a new frame starts, until a valid pointer is found. This bit is set at each attempt that fails
even if it has not had a successful pointer read since it has been cleared.
Write a one to clear this bit.
0: Buffer is available.
1: Buffer is not available because an attempt was made to get a new buffer and the pointer indicated that it was owned by the
processor.
Receive Status Register
30
22
14
6
-
-
-
-
RSR
Read/Write
0x20
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
OVR
26
18
10
2
-
-
-
REC
25
17
9
1
-
-
-
AT32UC3C
BNA
24
16
8
0
-
-
-
516