AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 574

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
the TXSYNH in the THR register. The USART character format is modified and includes sync
information.
of a user-defined pattern that indicates the beginning of a valid data.
these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a
logic zero is Manchester encoded and indicates that a new character is being sent serially on the
line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at
0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character.
The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the
middle of the second bit time. Two distinct sync patterns are used: the command sync and the
data sync. The command sync has a logic one level for one and a half bit times, then a transition
to logic zero for the second one and a half bit times. If the MODSYNC field in the MR register is
set to 1, the next character is a command. If it is set to 0, the next character is a data. When
direct memory access is used, the MODSYNC field can be immediately updated with a modified
character located in memory. To enable this mode, VAR_SYNC field in MR register must be set
to 1. In this case, the MODSYNC field in MR is bypassed and the sync configuration is held in
Figure 25-8. Preamble Patterns, Default Polarity Assumed
A start frame delimiter is to be configured using the ONEBIT field in the MR register. It consists
Manchester
Manchester
Manchester
Manchester
encoded
encoded
encoded
encoded
data
data
data
data
Txd
Txd
Txd
Txd
8 bit width "ZERO_ONE" Preamble
8 bit width "ONE_ZERO" Preamble
8 bit width "ALL_ZERO" Preamble
8 bit width "ALL_ONE" Preamble
Figure 25-9
AT32UC3C
SFD
SFD
SFD
SFD
DATA
DATA
DATA
DATA
illustrates
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