AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 968

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
The PWM internal clock (named CCK and driven either by CLK_PWM or by GCLK) is divided in
the clock generator module to provide different clocks available for all channels. Each channel
can independently select one of the divided clocks.
The selection of the source clock of the PWM counters is made by the CLKSEL bit in the CLK
Register. In asynchronous clocking mode (CLKSEL=1, GCLK selected), the PWM counters and
the prescaler allow running the CPU from any clock source while the prescaler is operating on a
faster clock (GCLK).
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies
that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “CCK”. This sit-
uation is also true when the PWM master clock is turned off through the Power Management
Controller.
CAUTION :
• Before using the PWM, the programmer must first enable the PWM clock in the Power
• The master clock frequency (CLK_PWM) must be lower than half of the generic clock
• After selecting a new PWM input clock (written CLKSEL to a new value), no write in any
Manager (PM).
frequency (GCLK) due to the synchronization mechanism between both clock domains.
PWM registers must be attempted before a delay of 2 master clock periods (CLK_PWM).
This is the time needed by the PWM to switch the source of the internal clock (CCK).
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and
F
clkB
CCK
/32, F
CCK
/64, F
CCK
/128, F
CCK
/256, F
CCK
/512, F
CCK
, F
CCK
CCK
/1024
/2, F
CCK
/4, F
AT32UC3C
CCK
/8, F
CCK
/16,
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