AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 654

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.8
25.8.1
32117C–AVR-08/11
Module Configuration
Clock Connections
The specific configuration for each USART instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
Table 25-26. Module Configuration
Table 25-27. Module Clock Name
Each USART can be connected to an internally divided clock:
Table 25-28. USART Clock Connections
Feature
ISO7816
IRDA Logic
RS485 Logic
Modem Logic
SPI Logic
LIN Logic
Manchester Logic
Fractional Baudrate
DIV value for divided CLK_USART
Receiver Time-out Counter Size
(Size of the RTOR.TO field)
Module name
USART0
USART1
USART2
USART3
USART4
USART
0
1
2
3
4
Clock name
CLK_USART0
CLK_USART1
CLK_USART2
CLK_USART3
CLK_USART4
Source
Internal
Name
CLK_DIV
USART0
USART2
USART3
USART4
Not Implemented
Not Implemented
Not Implemented
Not Implemented
Implemented
Implemented
Not Implemented
Implemented
8
17-bits
Description
Peripheral Bus clock from the PBA clock domain
Peripheral Bus clock from the PBC clock domain
Peripheral Bus clock from the PBA clock domain
Peripheral Bus clock from the PBA clock domain
Peripheral Bus clock from the PBC clock domain
Connection
PBA Clock / 8 (CLK_PBA_USART_DIV)
PBC Clock / 8 (CLK_PBC_USART_DIV)
PBA Clock / 8 (CLK_PBA_USART_DIV)
PBA Clock / 8 (CLK_PBA_USART_DIV)
PBC Clock / 8 (CLK_PBC_USART_DIV)
USART1
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
8
17-bits
AT32UC3C
654