AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 512

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.7.4
Name:
Access Type:
Offset:
Reset Value:
This register, when read, returns details of the status of a transmit. Once read, individual bits may be cleared by writing a
one to them. It is not possible to write a bit to one by writing to the register.
• UND: Transmit Underrun
• COMP: Transmit Complete
• BEX:
• TGO: Transmit Go
• RLE: Retry Limit Exceeded
32117C–AVR-08/11
31
23
15
7
-
-
-
-
Buffers Exhausted Mid Frame
This bit is set when transmit DMA was not able to read data from memory, either because the bus was not granted in time or
because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad CRC.
Write a one to clear this bit.
0: No transmit underrun.
1: Transmit underrun.
This bit is set when a frame has been transmitted.
Write a one to clear this bit.
0: Transmit is not completed.
1: Transmit is completed.
This bit is set if the buffers run out during transmission of a frame. Then transmission stops, FCS shall be bad and TX_ER is
asserted.
Write a one to clear to this bit.
0: Buffer is not exhausted.
1: Buffer is exhausted.
0: Transmit is inactive.
1: Transmit is active.
This bit is set when retry limit has exceeded.
Write a one to clear this bit.
0: Retry limit is not exceeded.
Transmit Status Register
UND
30
22
14
6
-
-
-
TSR
Read/Write
0x14
0x00000000
COMP
29
21
13
5
-
-
-
BEX
28
20
12
4
-
-
-
TGO
27
19
11
3
-
-
-
RLE
26
18
10
2
-
-
-
COL
25
17
9
1
-
-
-
AT32UC3C
UBR
24
16
8
0
-
-
-
512