AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1051

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.6.1.4
34.6.1.5
34.6.1.6
34.6.1.7
Figure 34-5. Quadrature Clock and Direction Decoding (TOP.PCTOP = 4)
32117C–AVR-08/11
Position counter
Index detection
Revolution counter
Waveforms
CNTDIR
QPulse
QEPA
QEPB
The 16-bit position counter is incremented or decremented on every count pulse, generated by
the quadrature decoder module. The counting direction is displayed in SR.CNTDIR.
If the position counter reaches the TOP.PCTOP value when counting up or the 0 value when
counting down, the counter wraps around. The Position Counter Roll Over (PCRO) interrupt is
generated.
Usually, the TOP.PCTOP value should always be set to the total number of quadrature states
minus one, which is (quadrature_encoder_lines_count *4) -1.
The optional index signal QEPI may be used to correct the position counter if quadrature states
have been missed due to noise. If the Index Enable bit (CF.IDXE) is written to one, detection of
the QEPI signal will reset the position counter to 0 on a selected phase of quadrature signals.
This selected phase is configured via the Detection Phase field (CF.IDXPHS).
The Index Error (IDXERR) interrupt is triggered if the index detection occurs and the position
counter value is not 0.
The revolution counter is incremented/decremented each time the position counter rolls over. It
rolls over when it reaches the TOP.RCTOP value.
PC
RC
0
1
0
2
3
4
0
1
1
2
1
0
4
3
0
2
1
AT32UC3C
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