AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 366

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.8.5
Register Name:
Access Type:
Offset:
Reset Value:
• TIMEOUT: Time to Define when Low Power Mode Is Enabled
• DS: Drive Strength (only for low power SDRAM)
• TCSR: Temperature Compensated Self Refresh (only for low power SDRAM)
• PASR: Partial Array Self Refresh (only for low power SDRAM)
32117C–AVR-08/11
TIMEOUT
31
23
15
7
-
-
-
-
0
1
2
3
This field is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be
set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its DS parameter value is updated before entry in self refresh mode.
This field is transmitted to the SDRAM during initialization to set the refresh interval during self refresh mode depending on the
temperature of the low power SDRAM. This parameter must be set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its TCSR parameter value is updated before entry in self refresh mode.
This field is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. This parameter must be set according to the
SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its PASR parameter value is updated before entry in self refresh mode.
Low Power Register
Time to Define when Low Power Mode Is Enabled
The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer.
The SDRAMC activates the SDRAM low power mode 64 clock cycles after the end of the last transfer.
The SDRAMC activates the SDRAM low power mode 128 clock cycles after the end of the last transfer.
Reserved.
30
22
14
6
-
-
-
LPR
Read/Write
0x10
0x00000000
PASR
29
21
13
5
-
-
TIMEOUT
28
20
12
4
-
-
27
19
11
3
-
-
-
DS
26
18
10
2
-
-
-
25
17
9
1
-
-
AT32UC3C
TCSR
LPCB
24
16
8
0
-
-
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