AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 487

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24. Ethernet MAC (MACB)
24.1
24.2
32117C–AVR-08/11
Features
Overview
Rev: 1.1.2.0
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The MACB module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 stan-
dard using an address checker, statistics and control registers, receive and transmit sub-
modules, and a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
ter for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register sub-module contains registers for counting various types of events associ-
ated with transmit and receive operations. These registers, along with the status words stored in
the receive buffer list, enable software to generate network management statistics compatible
with IEEE 802.3.
Compatible with IEEE Standard 802.3
10 and 100 Mbit/s Operation
Full- and Half-duplex Operation
Statistics Counter Registers
MII/RMII Interface to the Physical Layer
Interrupt Generation to Signal Receive and Transmit Completion
DMA Master on Receive and Transmit Channels
Transmit and Receive FIFOs
Automatic Pad and CRC Generation on Transmitted Frames
Automatic Discard of Frames Received with Errors
Address Checking Logic Supports Up to Four Specific 48-bit Addresses
Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
Hash Matching of Unicast and Multicast Destination Addresses
External Address Matching of Received Frames
Physical Layer Management through MDIO Interface
Half-duplex Flow Control by Forcing Collisions on Incoming Frames
Full-duplex Flow Control with Recognition of Incoming Pause Frames and Hardware
of Transmitted Pause Frames
Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and
Frames
Multiple Buffers per Receive and Transmit Frame
Wake-on-LAN Support
Jumbo Frames Up to 10240 bytes Supported
Priority Tagged
AT32UC3C
Generation
487