AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 980

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.6.2.8
Figure 33-10. Method 1 (UPDM=0)
32117C–AVR-08/11
UPDULOCK
CDTYUPD
Method 1: Manual write of duty-cycle values and manual trigger of the update
CCNT0
CDTY
0x20
0x20
In this mode, the update of the period value, the duty-cycle values and the dead-time values
must be made by writing in their respective update registers with the CPU (respectively CPR-
DUPDx, CDTYUPDx and DTUPDx).
To trigger the update, the user must use the UPDULOCK bit of the
trol Register” on page 1007
period) the synchronous channels:
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read
0.
Sequence for the Method 1:
• If the UPDULOCK bit is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
1. Select the manual write of duty-cycle values and the manual update by writing the
2. Define the synchronous channels by the SYNCx bits in the SCM register.
3. Enable the synchronous channels by writing CHID0 in the ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time val-
5. Write UPDULOCK to one in SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this
synchronous channels.
UPDM field to zero in the SCM register
ues is required, write registers that need to be updated (CPRDUPDx, CDTYUPDx and
DTUPDx).
time the UPDULOCK bit is reset, go to step 4) for new values.
0x40
0x40
0x60
(SCUC) which allows to update synchronously (at the same PWM
0x60
”Sync Channels Update Con-
AT32UC3C
980