AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1149

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.4
37.5
37.5.1
37.5.2
37.5.3
37.5.4
37.5.5
37.5.6
32117C–AVR-08/11
I/O Lines Description
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Peripheral Events
Debug Operation
Table 37-1.
The pins used for interfacing the DAC may be multiplexed with GPIO lines. The programmer
must first program the GPIO controller to assign the desired DAC pins to their peripheral func-
tion. If I/O lines of the DAC are not used by the application, they can be used for other purposes
by the GPIO controller.
If the CPU enters a sleep mode that disables CLK_DACIFB used by the DACIFB, the DACIFB
will stop functioning and will resume operation after the system wakes up from sleep mode.
The DACIFB is clocked through the Power Manager (PM), therefore the programmer must first
configure the PM to enable the CLK_DACIFB clock.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the DACIFB before disabling the clock, to avoid freezing the DACIFB in an undefined
state.
The DACIFB interrupt lines are connected to the internal sources of the interrupt controller.
Using the DACIFB interrupts requires the interrupt controller to be programmed first.
The DACIFB peripheral events are connected via the Peripheral Event Controller. Refer to the
Peripheral Event Controller chapter for details.
The DACIFB is disabled during debug operation, unless the Run In Debug bit in the Develop-
ment Control Register is set and the bit corresponding to the DACIFB is set in the Peripheral
Debug Register (PDBG). Please refer to the On-Chip Debug chapter in the AVR32UC Technical
Reference Manual, and the OCD Module Configuration section, for details.
The DACIFB is debug-mode aware. When the CPU is in debug mode, all the incoming triggers
are blocked, therefore all DMA based conversions are halted upon debug mode activation. The
auto-refresh functionality is kept active so that the last converted value remains visible on both
channels outputs.
Apart from the auto-trig mode, it is possible to perform “one shot” conversions triggered by write
accesses to the data register.
Pin Name
DACA
DACB
DACREF
I/O Lines Description
Pin Description
DAC voltage reference
DAC channel A analog output
DAC channel B analog output
Type
Output
Output
Input
Active Level
N/A
N/A
N/A
AT32UC3C
1149