AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1055

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.6.4
32117C–AVR-08/11
Peripheral Events
Each interrupt source can be enabled by writing a one to the corresponding bit in the Interrupt
Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Dis-
able Register (IDR). The enable status can be read from the Interrupt Mask Register (IMR). The
status of the interrupt sources, even if the interrupt is masked, can be read in SR. When an inter-
rupt has occurred, it is reset by writing a one to the corresponding bit in the Status Clear
Register (SCR).
The QDEC can receive three peripheral events from the Peripheral Event Controller (PEVC):
The QDEC can send one event to the PEVC:
The PEVC must be programmed to enable QDEC peripheral events.
• The RCRO interrupt to detect a roll-over of the revolution counter.
• The IDXERR interrupt to detect that the index signal (QEPI) is detected and the position
• The DIRINV interrupt occurs when the count direction changes.
• The QDERR interrupt occurs when a bad transition in the quadrature signals is detected (for
• The TRIGGER interrupt occurs when a trigger event from PEVC is detected. It could be used
•
• The trigger peripheral event starts CLK_QDEC_INT and enables the counter.
• The capture peripheral event captures CNT in the Capture register (CAP).
• The toggle_dir peripheral event toggles the count direction when the QDEC works in Timer
• The compare peripheral event when the CNT register reaches the Compare register (CMP)
counter does not have the expected value (TOP.PCTOP if the counter counts up, 1 if the
counter counts down).
example, from “00” to “11”). This could be caused by erroneous programming of the
GCLK_QDEC frequency.
by software to detect a reset of the counters.
mode with UPD mode active.
value.
AT32UC3C
1055