AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 80

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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7.8
Table 7-14.
32117C–AVR-08/11
CPU/HSB/PBx
(excluding Power Manager)
32 KHz oscillator
AST registers, except interrupt
registers
GPLP registers
Watchdog control register
Voltage Regulator Calibration
register
RCSYS Calibration register
1.8V BOD control register
3.3V BOD control register
Bandgap control register
Clock control registers
OSC control registers
OCD system and OCD registers
Module Configuration
Effect of the different Reset Events
The specific configuration for each PM instance is listed in the following tables. The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 7-12.
Table 7-13.
Module name
PM
Register
CONFIG
VERSION
Power-On
Reset
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Module clock name
Register Reset Values
Clock name
CLK_PM
Reset Value
0x00000087
0x00000412
External
Reset
Y
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
Watchdog
Reset
Y
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
Description
Peripheral Bus clock from the PBA clock domain
1.8V
BOD
Reset
Y
N
N
N
Y
N
N
N
Y
N
Y
Y
Y
3.3V
BOD
Reset
Y
N
N
N
Y
N
N
Y
N
Y
Y
Y
Y
N
Y
N
Y
Y
Y
CPU
Error
Reset
Y
N
N
N
Y
Y
Y
OCD
Reset
Y
N
N
N
Y
N
N
Y
Y
Y
Y
Y
N
AT32UC3C
JTAG
Reset
Y
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
Awire
Reset
Y
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
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