AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 987

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 33-15. Comparison Waveform
32117C–AVR-08/11
Comparison Update
Comparison Match
CVMVUPD
CUPRUPD
CUPRCNT
CTRUPD
CPRUPD
CPRCNT
CVUPD
CCNT0
CMPM
CMPU
CUPR
CVM
CPR
CTR
CV
0x6
0x1
0x1
0x3
0x6
0x1
0x1
0x3
0x0
0x0
The update of the comparison x configuration and the comparison x value is triggered periodi-
cally after the comparison x update period. It is defined by the CUPR field in the CMPxM. The
comparison unit has an update period counter independent from the period counter to trigger
this update. When the value of the comparison update period counter CUPRCNT (in CMPxM)
reaches the value defined by CUPR, the update is triggered. The comparison x update period
CUPR itself can be updated while the channel 0 is enabled by using the CMPxMUPD register.
CAUTION: to be taken into account, writing in the CMPxVUPD register must be followed by a
write in the CMPxMUPD register.
The comparison match and the comparison update can be a source of an interrupt, but only if it
is enabled and not masked. These interrupts can be enabled by the
2” on page 1010
son match interrupt and the comparison update interrupt are reset by reading the
Status Register 2” on page
0x1
0x1
0x2
0x2
0x0
0x2
0x3
0x2
and disabled by the
0x3
0x1
1013.
0x2
0x2
0x0
0x3
0x2
0x0
0x1
0x1
”Interrupt Disable Register 2” on page
0x2
0x2
0x0
0x3
0x6
0x1
0x0
0x2
0x1
”Interrupt Enable Register
0x6
0x0
0x2
AT32UC3C
1011. The compari-
0x1
0x3
”Interrupt
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