AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 314

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.6.4.2
32117C–AVR-08/11
Read mode
•Read is controlled by NRD (MODE.READMODE = 1)
Figure 18-8. No Setup, No Hold on NRD, and NCS Read Signals
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
i n g s t o k n o w w h i c h s ig n a l r i s e s f i r s t . T h e R e a d M o d e b it i n t h e M O D E r e g i s t e r
(MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS
controls the read operation.
Figure 18-9 on page 315
RAM. The read data is available t
ing edge of NRD. In this case, the MODE.READMODE bit must be written to one (read is
controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC sam-
ples the read data internally on the rising edge of CLK_SMC that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
• Null Pulse
NBS0, NBS1,
A[AD_MSB:2]
A0, A1
CLK_SMC
D[15:0]
NRD
NCS
NRDSETUP
NCSRDPULSE
NRDCYCLE
shows the waveforms of a read operation of a typical asynchronous
PACC
after the falling edge of NRD, and turns to ‘Z’ after the ris-
NRDPULSE
NCSRDPULSE
NRDCYCLE
NRDCYCLE
NRDPULSE
NCSRDPULSE
AT32UC3C
314