AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1064

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.7.7
Name:
Access Type:
Offset:
Reset Value:
• CLKEN: QDEC Counter Clock Status
• CNTDIR: Counter Direction
• TRIGGER: Trigger Event Occurrence
• QDERR: Illegal Quadrature Signals Transition
• OVR: Overrun Capture
• DIRINV: Count Direction Inversion
• IDXERR: Index Error
• RCRO: Revolution Counter Roll Over
• PCRO: Position Counter Roll Over
32117C–AVR-08/11
OVR
31
23
15
-
-
-
7
This bit is cleared when the QDEC and CLK_QDEC_INT has been disabled
This bit is set when the QDEC and CLK_QDEC_INT has been enabled
This bit is cleared when the counter counts up
This bit is set when the counter counts down
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the trigger event has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an illegal transition of quadrature signals has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the overrun capture event has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the count direction has changed
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an index error has occurred
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the revolution counter has rolled over
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when the position counter has rolled over
Status Register
DIRINV
30
22
14
SR
Read-only
0x1C
0x00000000
–
-
-
6
IDXERR
29
21
13
-
-
–
5
RCRO
28
20
12
-
-
–
4
PCRO
27
19
11
-
-
–
3
CAP
26
18
10
-
-
–
2
TRIGGER
CLKEN
CMP
25
17
–
9
1
AT32UC3C
CNTDIR
QDERR
QEPI
24
16
–
8
0
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