AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 936

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.2.14
Register Name:
Access Type:
Offset:
Reset Value:
• BUSY0E: Busy Bank0 Enable
• BUSY1E: Busy Bank1 Enable
• STALLRQ: STALL Request
• RSTDT: Reset Data Toggle
• FIFOCON: FIFO Control
32117C–AVR-08/11
31
23
15
7
-
-
-
-
This bit is cleared when the BUSY0C bit is written to one.
This bit is set when the BUSY0ES bit is written to one. This will set the bank 0 as “busy”. All transactions, except SETUP,
destined to this bank will be rejected (i.e: NAK token will be answered).
This bit is cleared when the BUSY1C bit is written to one.
This bit is set when the BUSY1ES bit is written to one. This will set the bank 1 as “busy”. All transactions, except SETUP,
destined to this bank will be rejected (i.e: NAK token will be answered).
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
This bit is set when the STALLRQS bit is written to one, requesting a STALL handshake to be sent to the host.
The data toggle sequence is cleared when the RSTDTS bit is written to one (i.e., Data0 data toggle sequence will be selected
for the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is always read as zero.
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them for these endpoints. When read,
their value is always 0.
For IN endpoints:
This bit is cleared when the FIFOCONC bit is written to one, sending the FIFO data and switching to the next bank.
This bit is set simultaneously to TXINI, when the current bank is free.
For OUT endpoints:
This bit is cleared when the FIFOCONC bit is written to one, freeing the current bank and switching to the next.
This bit is set simultaneously to RXINI, when the current bank is full.
Endpoint n Control Register
STALLEDE/
CRCERRE
FIFOCON
30
22
14
6
-
-
UECONn, n in [0..6]
Read-Only
0x01C0 + (n * 0x04)
0x00000000
KILLBK
29
21
13
5
-
-
-
NBUSYBKE
NAKINE
28
20
12
4
-
-
RAMACERE
NAKOUTE
STALLRQ
27
19
11
3
-
ERRORFE
RXSTPE/
RSTDT
26
18
10
2
-
-
RXOUTE
BUSY1E
25
17
9
1
-
-
AT32UC3C
BUSY0E
TXINE
24
16
8
0
-
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