AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 57

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6.5.1
7.6.5.2
7.6.6
7.6.7
32117C–AVR-08/11
Clock Failure Detector
Interrupts
Power-On Detector
External Reset
The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the
device is powered on. The reset is active until the supply voltage from the linear regulator is
above the power-on threshold level. The reset will be re-activated if the voltage drops below the
power-on threshold level. See Electrical Characteristics for parametric details.
The external reset detector monitors the state of the RESET_N pin. By default, a low level on
this pin will generate a reset.
This mechanism allows switching the main clock to the safe RCSYS clock, when the main clock
source is considered off. This may happen when a external crystal is selected as the clock
source of the main clock but the crystal is not mounted on the board. The mechanism is to
detect, during a RCSYS period, at least one rising edge of the main clock. If no rising edge is
seen the clock is considered failed.
Example:
* RCSYS = 115khz
=> Failure detected if the main clock is < 115 kHz
As soon as the detector is enabled, the clock failure detector will monitor the divided main clock.
Note that the detector does not monitor if the RCSYS is the source of the main clock, or if the
main clock is temporarily not available (startup-time after a wake-up, switching timing etc.), or in
sleep mode where the main clock is driven by the RCSYS (Stop and DeepStop mode). When a
clock failure is detected, the main clock automatically switches to the RCSYS clock and the CFD
interrupt is generated if enabled.
The MCCTRL register that selects the source clock of the main clock is changed by hardware to
indicate that the main clock comes from RCSYS.
The PM has a number of interrupts:
• AE: Access Error, set if a lock protected register is written without first being unlocked.
• CKRDY: Clock Ready, set when new CKSEL settings are effective.
• CFD: Clock Failure Detected, set if the system detects that the main clock is not running.
AT32UC3C
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