AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 802

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30. Inter-IC Sound Controller (IISC)
30.1
30.2
32117C–AVR-08/11
Features
Overview
Rev.: 2.0.0.0
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The Inter-IC Sound Controller (IISC) provides a 5-wire, bidirectional, synchronous, digital audio
link with external audio devices: ISDI, ISDO, IWS, ISCK, and IMCK pins.
This controller is compliant with the Inter-IC Sound (I
interface with external multi-channel audio codecs.
The IISC consists of a Receiver, a Transmitter, and a common Clock Generator, that can be
enabled separately, to provide Master, Slave, or Controller modes with Receiver, Transmitter, or
both active.
Peripheral DMA channels, separate for the Receiver and for the Transmitter, allow a continuous
high bitrate data transfer without processor intervention to the following:
The IISC can use either a single DMA channel for all audio channels or one DMA channel per
audio channel.
The 8- and 16-bit compact stereo format allows reducing the required DMA bandwidth by trans-
ferring the left and right samples within the same data word.
In Master Mode, the IISC allows outputting a 16 fs to 1024fs Master Clock, in order to provide an
oversampling clock to an external audio codec or digital signal processor (DSP).
• Audio CODECs in Master, Slave, or Controller mode
• Stereo DAC or ADC through dedicated I
• Multi-channel or multiple stereo DACs or ADCs, using the TDM format
Compliant with Inter-IC Sound (I
Master, slave, and controller modes:
Individual enable and disable of receiver, transmitter, and clocks
Configurable clock generator common to receiver and transmitter:
Several data formats supported:
Several data frame formats supported:
DMA interfaces for receiver and transmitter to reduce processor overhead:
Smart holding registers management to avoid audio channels mix after overrun or underrun
– Slave: data received/transmitted
– Master: data received/transmitted and clocks generated
– Controller: clocks generated
– Suitable for a wide range of sample frequencies (fs), including 32kHz, 44.1kHz, 48kHz,
– 16fs to 1024fs Master Clock generated for external oversampling ADCs
– 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
– 16- and 8-bit compact stereo format, with left and right samples packed in the same word to
– 2-channel I
– 1- to 8-channel Time Division Multiplexed (TDM) with Frame Sync
– Either one DMA channel for all audio channels, or
– One DMA channel per audio channel
88.2kHz, 96kHz, and 192kHz
reduce data transfers
2
S with Word Select
2
S) bus specification
2
S serial interface
2
S) bus specification and supports TDM
AT32UC3C
802