AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 986

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.6.3
32117C–AVR-08/11
PWM Comparison Units
The PWM provides 8 independent comparison units able to compare a programmed value with
the current value of the channel 0 counter (which is the channel counter of all synchronous
channels,
on the event lines (used to synchronize ADC, see
ware interrupts and to trigger PDCA transfer requests for the synchronous channels (see
Section 33.6.2.10 on page
Figure 33-14. Comparison Unit Block Diagram
The comparison x matches when it is enabled by the CEN bit in the
ter” on page 1033
reaches the comparison value defined by the CV field in
1031
”Channel Mode Register” on page
made when the counter is counting up or counting down (in left alignment mode CALG=0, this
bit is useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see
33.6.2.6 on page
The user can define the periodicity of the comparison x by the CTR and CPR fields (in CMPxV).
The comparison is performed periodically once every CPR+1 periods of the counter of the chan-
nel 0, when the value of the comparison period counter CPRCNT (in CMPxM) reaches the value
defined by CTR. CPR is the maximum value of the comparison period counter CPRCNT. If
CPR=CTR=0, the comparison is performed at each period of the counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the
”PWM Comparison x Mode Update Register” on page 1034
parison x). In the same way, the comparison x value can be modified while the channel 0 is
enabled by using the
ters for the comparison x).
(CMPxV for the comparison x). If the counter of the channel 0 is center aligned (CALG=1 in
Section 33.6.2.7 on page
CEN [PWM_CMPxM]
fault on channel 0
CV [PWM_CMPxV]
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CVM [PWM_CMPxV]
CALG [PWM_CMR0]
CPRCNT [PWM_CMPxM]
CTR [PWM_CMPxM]
976).
(CMPxM for the comparison x) and when the counter of the channel 0
”Comparison x Value Update Register” on page 1032
983).
1035), the CVM bit (in CMPxV) defines if the comparison is
978). These comparisons are intended to generate pulses
=
=
=
1
Section 33.6.4 on page
0
1
”Comparison x Value Register” on page
(CMPxMUPD registers for the com-
”Comparison x Mode Regis-
Comparison x
988), to generate soft-
AT32UC3C
(CMPxVUPD regis-
Section
986