AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 894

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.6.3.7
32.6.3.8
32117C–AVR-08/11
Remote wakeup
RAM management
Writing UHCON.SOFE to zero when in host mode will cause the USBC to cease sending SOF’s
on the USB bus and enter the Suspend state. The USB device will enter the Suspend state 3ms
later.
The device can awaken the host by sending an Upstream Resume (remote wakeup feature).
When the host detects a non-idle state on the USB bus, it sets the Host Wakeup interrupt bit
(UHINT.HWUPI). If the non-idle bus state corresponds to an Upstream Resume (K state), the
Upstream Resume Received Interrupt bit (UHINT.RXRSMI) is set and the user has to generate
a Downstream Resume within 1ms and for at least 20ms. It is required to first enter the Ready
state by writing a one to UHCON.SOFEF and then writing a one to the Send USB Resume bit
(UHCON.RESUME).
Pipe data can be physically allocated anywhere in the embedded RAM. The USBC controller
accesses the pipes directly through the HSB master (built-in DMA).
The USBC controller reads the USBC descriptors to know the location of each pipe. The base
address of this USBC descriptor (UDESC.UDESCA) needs to be written by the user. The
descriptors can also be allocated anywhere in the embedded RAM.
Before using a pipe, the user should setup the data address for each bank. Depending on the
direction, pipe type, targeted device address, targeted endpoint number, and packet-mode (sin-
gle or multi-packet), the user should also initialize the pipe packet size and the pipe control and
status field, so that the USB controller does not compute random values from the RAM.
When using a pipe, the user should read the UPSTAX.CURRBK field to know which bank is cur-
rently processed.
AT32UC3C
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