AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 889

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
RXOUTI
FIFOCON
OUT
• Detailed description
• Multi packet mode for OUT endpoints
(bank 0)
DATA
Figure 32-15. Example of an OUT endpoint with two data banks
Before using the OUT endpoint, one should properly initialize its descriptor for each bank. See
Figure 32-8 on page
The data is read, according to this sequence:
If the endpoint uses several banks, the current one can be read while the next is being written by
the host. When the user clears FIFOCON, the following bank may already be ready and RXOUTI
will be immediately set.
In multi packet mode, the user can extend the size of the bank allowing the storage of n USB
packets in the bank.
To enable the multi packet mode, the user should configure the endpoint descriptor
(EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE) to match the size of the multi packet.This value
should be a multiple of the endpoint size (UECFGn.EPSIZE).
Since the EPn_PCKSIZE_BK0/1.BYTE_COUNT is incremented (by the received packet size)
after each successful transaction, it should be set to zero when setting up a new multi packet
transfer.
As for single packet mode, the number of received data bytes is stored in the BYTE_CNT field.
The bank is considered as “valid” and the RX_OUT flag is set when:
• When the bank is full, RXOUTI and FIFOCON are set, which triggers an EPnINT interrupt if
• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.
• The user reads the UESTAX.CURRBK field to know the current bank number.
• The user reads the byte count of the current bank from the descriptor in RAM
• The user reads the data in the current bank, located in RAM as described by its descriptor:
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
RXOUTE is one.
(EPn_PCKSIZE_BK0/1.BYTE_COUNT) to know how many bytes to read.
EPn_ADDR_BK0/1.
ACK
HW
SW
882.
OUT
read data from CPU
BANK 0
(bank 1)
DATA
ACK
HW
SW
AT32UC3C
read data from CPU
SW
BANK 1
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