AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 990

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.6.5.2
33.6.5.3
33.6.5.4
32117C–AVR-08/11
Changing the Duty-Cycle, the Period and the Dead-Times
Changing the Synchronous Channels Update Period
Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the
value in the
Register” on page 1037
ister gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value.
The higher the value of CPRDx, the greater the PWM accuracy.
For example, if the user writes 15 (in decimal) in CPRDx, the user is able to write a value
between 1 up to 14 in CDTYx Register. The resulting duty-cycle quantum cannot be lower than
1/15 of the PWM period.
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the
Register” on page
Dead Time Update Register” on page 1045
waveform parameters while the channel is still enabled.
Note:
It is possible to change the update period of synchronous channels (see
page 981
To prevent an unexpected update of the synchronous channels registers, the user must use the
”Sync Channels Update Period Update Register” on page 1009
update period of synchronous channels while they are still enabled. This register holds the new
value until the end of the update period of synchronous channels (when UPRCNT is equal to
• If the channel is an asynchronous channel (SYNCx=0 in
• If the channel is a synchronous channel and update method 0 is selected (SYNCx=1 and
• If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and
page 1005
until the end of the current PWM period and update the values for the next period.
UPDM=0 in SCM register), these registers hold the new period, duty-cycle and dead-times
values until the UPDULOCK bit is written to one (in
on page 1007
the next period.
UPDM=1 or 2 in SCM register):
– these CPRDUPDx and DTUPDx registers hold the new period and dead-times
– the CDTYUPDx register holds the new duty-cycle value until the end of the update
values until the UPDULOCK bit is written to one (in SCUC register) and the end of
the current PWM period, then update the values for the next period.
period of synchronous channels (when UPRCNT is equal to UPR in
Update Period Register” on page 1008
period, then updates the value for the next period
If the update registers (CDTYUPDx, CPRDUPDx and DTUPDx) are written several times between
two updates, only the last written value is taken into account.
and
”Channel Period Register” on page 1039
Section 33.6.2.10 on page
(SCM)), these registers hold the new period, duty-cycle and dead-times values
(SCUC)) and the end of the current PWM period, then update the values for
1038, the
(CDTYx) can help the user. The event number written in the Period Reg-
”Channel Period Update Register” on page 1041
983) while they are enabled.
(CDTYUPDx, CPRDUPDx and DTUPDx) to change
(SCUP)) and the end of the current PWM
”Sync Channels Update Control Register”
(CPRDx) and the
”Sync Channels Mode Register” on
”Channel Duty Cycle Update
(SCUPUPD) to change the
”Channel Duty Cycle
AT32UC3C
”Sync Channels
Section 33.6.2.9 on
and the
”Channel
990