AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 104

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

7.3.4 TX Output Power
7.3.5 TX Power Ramping
Figure 7-9. TX Power Ramping Example (O-QPSK 250 kbit/s Mode)
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AT86RF212
Figure 7-4 to Figure 7-8 illustrate typical spectra of the transmitted signals of the
AT86RF212 and do not claim any limits.
Refer to the local authority bodies (FCC, ETSI, etc.) for further details about definition of
power spectral density masks, definition of spurious emission, allowed modulation
bandwidth, transmit power, and its limits.
The maximum output power of the transmitter is typically 5 dBm in normal mode and 10
dBm in boost mode. The TX output power can be set via register bits TX_PWR (register
0x05, PHY_TX_PWR). The output power of the transmitter can be controlled down to
-11 dBm dB with 1 dB resolution.
To meet the spectral requirements of the European and Chinese bands, it is necessary
to limit the TX power by appropriate setting of TX_PWR, GC_PA (register 0x05,
PHY_TX_PWR), and GC_TX_OFFS (register 0x16, TX_CTRL_0). See Table 7-15 and
Table 7-16 for recommended values.
To optimize the output power spectral density (PSD), individual transmitter blocks are
enabled sequentially. A transmit action is started by either the rising edge of pin
SLP_TR or the command TX_START in register 0x02. One symbol period later the data
transmission begins. During this time period, the PLL settles to the frequency used for
transmission. The PA is enabled prior to the data transmission start. This PA lead time
can be adjusted with the value PA_LT in register 0x16 (RF_CTRL_0). The PA is always
enabled at the lowest gain value corresponding to GC_PA = 0. Then the PA gain is
increased automatically to the value set by GC_PA in register 0x16 (RF_CTRL_0). After
transmission is completed, TX power ramping down is performed in an inverse order.
The control signals associated with TX power ramping are shown in Figure 7-9. In this
example, the transmission is initiated with the rising edge of pin 11 (SLP_TR). The radio
transceiver state changes from PLL_ON to BUSY_TX.
Using an external RF front-end (refer to section 9.4), it may be required to adjust the
startup time of the external PA relative to the internal building blocks to optimize the
overall PSD. This can be achieved using register bits PA_LT (register 0x16,
RF_CTRL_0).
8168C-MCU Wireless-02/10