AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 136

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

9.1.5 Data Transfer – Fast SRAM Access
Figure 9-5. Packet Structure – Fast SRAM Access Mode
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AT86RF212
initialization vector is 0. However, for non-compliant usage any other initialization vector
can be used. This operation has to be prepared by the microcontroller.
Note that IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption
only, as it implements a one-way hash function.
The ECB and CBC modules, including the AES core, are clocked with 16 MHz. One
AES operation takes 24 µs to execute, refer to parameter 10.4.14 in section 10.4. This
means that the processing of the data is usually faster than the transfer of the data via
the SPI interface.
To reduce the overall processing time, the AT86RF212 provides a Fast SRAM access
for the address space 0x83 to 0x94. The Fast SRAM access allows writing and reading
of data simultaneously during one SPI access for consecutive AES operations (AES
run).
For each byte P0 transferred to pin 22 (MOSI), the previous content of the respective
AES register C0 is clocked out at pin 20 (MISO) with an offset of one byte. See Figure
9-5 as an example for “AES access #1”.
In the example shown in Figure 9-5 the initial plaintext P0 – P15 is written to the SRAM
within “AES access #0”. The last command on address 0x94 (AES_CTRL_MIRROR)
starts the AES operation (“AES run #0”). In the next “AES access #1” new plaintext data
P0 – P15 is written to the SRAM for the second AES run, in parallel the cipher text C0 –
last “AES run #(n)”, one dummy “AES access #(n+1)” is needed.
Note that the SRAM write access always overwrites the previous processing result.
The Fast SRAM access automatically applies to all write operations to SRAM
addresses 0x83 to 0x94.
C15 from the first AES run is clocked out at pin MISO. To read the cipher text from the
Note:
1. Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94;
see register description AES_CTRL_MIRROR for details.
8168C-MCU Wireless-02/10