AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 132

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

9 Extended Feature Set
9.1 Security Module (AES)
9.1.1 Overview
9.1.2 Security Module Preparation
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AT86RF212
The security module (AES) is characterized by:
• Hardware accelerated encryption and decryption
• Compatible with AES-128 standard (128 bit key and data block size)
• Support of ECB (encryption/decryption) mode and CBC (encryption) mode
• Stand-alone operation, independent of other blocks
The security module is based on an AES-128 core according to FIPS197 standard,
refer to [9]. The security module is independent from other building blocks of the
AT86RF212. Encryption and decryption can be performed in parallel to a frame
transmission or reception.
Controlling of the security block is implemented as an SRAM access to address space
0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and
reading data from previously processed data within the same SPI transfer. This access
procedure is used to reduce the turnaround time for ECB mode, see section 9.1.5.
In addition, the security module contains another 128-bit register to store the initial key
used for security operations. This initial key is not modified by the security module.
The use of the security module requires a configuration of the security engine before
starting a security operation. The required steps are listed in Table 9-1.
Table 9-1. AES Engine Configuration Steps
Before starting any security operation, a key must be written to the security engine. The
key set up requires the configuration of the AES engine KEY mode using register bits
AES_MODE (SRAM address 0x83, AES_CTRL). The following step selects the AES
mode, either electronic code book (ECB) or cipher block chaining (CBC). These modes
are explained in more detail in section 9.1.4. Further, encryption or decryption must be
selected with register bit AES_DIR (SRAM address 0x83, AES_CTRL).
After this, the 128-bit plain text or cipher text data has to be provided to the AES
hardware engine. The data uses the SRAM address range 0x84 – 0x93.
An encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM
address 0x83, i.e. AES_CTRL, or the mirrored version SRAM address 0x94, i.e.
AES_CTRL_MIRROR).
Step
1
2
3
4
5
Action
Key Setup
AES mode
Write Data
Start operation
Read Data
Description
Write encryption or decryption key to SRAM
Select AES mode: ECB or CBC
Select encryption or decryption
Write plaintext or cipher text to SRAM
Start AES operation
Read cipher text or plaintext from SRAM
8168C-MCU Wireless-02/10
Section
9.1.3
9.1.4
9.1.5
9.1.5