AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 27

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AT86RF212

Manufacturer Part Number
AT86RF212
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT86RF212

Max. Operating Frequency
0 MHz
Crypto Engine
AES
Operating Voltage (vcc)
1.8 to 3.6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120

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8168C-MCU Wireless-02/10
Register 0x0F (IRQ_STATUS):
The IRQ_STATUS register contains the status of the pending interrupt requests.
Table 4-17. Register 0x0F (IRQ_STATUS)
By reading the register after an interrupt is signaled at pin 24 (IRQ), the source of the
issued interrupt can be identified. A read access to this register resets all interrupt bits,
and so clears the IRQ_STATUS register.
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt
event can be read from IRQ_STATUS register, even if the interrupt itself is masked;
refer to Figure 4-18. However, in that case no timing information for this interrupt is
provided. It is recommended to read the interrupt status register 0x0F (IRQ_STATUS)
first to clear the history.
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
Table 4-18. Register 0x04 (TRX_CTRL_1)
• Bit 7 – PA_EXT_EN
RX/TX Indicator, refer to section 9.4.3.
• Bit 6 – IRQ_2_EXT_EN
The timing of a received frame can be determined by a separate pin. If register bit
IRQ_2_EXT_EN is set to 1, the reception of a PHR field is directly issued on
pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). Note that this pin is also active,
even if the corresponding IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK)
is set to 0. The pin remains at high level until the end of the frame receive procedure.
For further details refer to section 9.5.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
7
BAT_LOW
R
0
3
TRX_END
R
0
7
PA_EXT_EN
R/W
0
3
SPI_CMD_MODE
R/W
0
6
TRX_UR
R
0
2
RX_START
R
0
6
IRQ_2_EXT_EN
R/W
0
2
SPI_CMD_MODE
R/W
0
5
AMI
R
0
1
PLL_UNLOCK
R
0
5
TX_AUTO_CRC_ON
R/W
1
1
IRQ_MASK_MODE
R/W
0
AT86RF212
4
CCA_ED_DONE
R
0
0
PLL_LOCK
R
0
4
RX_BL_CTRL
R/W
0
0
IRQ_POLARITY
R/W
0
27

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