AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 141

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

9.3.3 Register Description
8168C-MCU Wireless-02/10
For transmission and reception, the antenna defined by register bits ANT_CTRL
(register 0x0D, ANT_DIV) is selected.
Figure 9-6. Antenna Diversity – Block Diagram
Register 0x0D (ANT_DIV):
The ANT_DIV register controls Antenna Diversity.
Table 9-11. Register 0x0D (ANT_DIV)
• Bit 7:3 – Reserved
• Bit 2 – ANT_EXT_SW_EN
If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential
control signal for an antenna diversity switch. The selection of a specific antenna is
done according to register bits ANT_CTRL.
If RX Frame Time Stamping (refer to section 9.5) is used in combination with Antenna
Diversity, DIG1 is used for Antenna Diversity and DIG2 is used for RX Frame Time
Stamping. AT86RF212 does not provide a differential control signal in this case, see
Figure 3-2.
If the register bit is set, the control pins DIG1/DIG2 are activated in all radio transceiver
states as long as register bit ANT_EXT_SW_EN is set. If the AT86RF212 is not in a
receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN
to reduce the power consumption or avoid leakage current of an external RF switch,
especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1
and DIG2 are internally connected to digital ground.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
7
Reserved
R
0
3
Reserved
R/W
0
6
Reserved
R
0
2
ANT_EXT_SW_EN
R/W
0
5
Reserved
R
0
1
ANT_CTRL[1]
R/W
0
AT86RF212
4
Reserved
R
0
0
ANT_CTRL[0]
R/W
1
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