AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 77

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

6.3 Frame Check Sequence (FCS)
6.3.1 Overview
6.3.2 CRC Calculation
8168C-MCU Wireless-02/10
• Bit 7:6 – AACK_FVN_MODE
The frame control field of the MAC header (MHR) contains a frame version subfield.
The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement
behavior of the AT86RF212. According to the content of these register bits, the radio
transceiver passes frames with a specific set of frame version numbers.
Thus, the register bit AACK_FVN_MODE defines the maximum acceptable frame
version. Received frames with a higher frame version number than configured do not
pass the Frame Filter and thus are not acknowledged.
Table 6-21. Frame Version Subfield dependent Frame Acceptance
• Bit 5:0
Refer to section 5.2.6.
A FCS mechanism employing a 16-bit International Telecommunication Union -
Telecommunication Standardization Sector (ITU-T) cyclic redundancy check (CRC) can
be used to detect errors in frames.
The FCS is intended for use at the MAC layer in order to detect corrupted frames. It is
computed by applying an ITU-T CRC polynomial to all transmitted/received bytes
following the length field (MHR and MSDU fields). The FCS has a length of 16 bit and is
located in the last two octets of the PSDU.
By default, the AT86RF212 generates and inserts the FCS octets autonomously during
transmit
TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1).
An automatic FCS check is always performed during frame reception.
The CRC polynomial used in IEEE 802.15.4 networks is defined by
The FCS shall be calculated for transmission using the following algorithm:
Let
Bit
Name
Read/Write
Reset Value
Register Bits
AACK_FVN_MODE
G
M
16
process.
(
(
x
x
)
3
AACK_I_AM_COORD
R/W
0
)
=
=
b
0
x
x
16
k
This
−
+
1
+
x
12
b
Value
1
x
behavior
+
0
1
2
3
k
x
−
2
5
+
2
CSMA_SEED_1
R/W
0
+
K
1
.
+
Description
Accept frames with version number 0
Accept frames with version number 0 or 1
Accept frames with version number 0 or 1 or 2
Accept frames independent of frame version number
can
b
k
−
2
x
be
+
b
k
−
disabled
1
1
CSMA_SEED_1
R/W
1
by
AT86RF212
setting
0
CSMA_SEED_1
R/W
0
register
77
bit