AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 17

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

Figure 4-6. Exemplary SPI Sequence – Register Access Mode
4.3.2 Frame Buffer Access Mode
Figure 4-7. Packet Structure - Frame Read Access
8168C-MCU Wireless-02/10
Figure 4-5. Register Access Mode – Write Access
Each register access must be terminated by setting /SEL = H. Figure 4-6 illustrates a
typical SPI sequence for a register write and read access.
The 128 byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or TX frame of maximum length at a time. A detailed
description of the Frame Buffer can be found in section 7.4. An introduction to the
IEEE 802.15.4 frame format can be found in section 6.1.
Frame Buffer read and write accesses are used to read or write frame data (PSDU and
additional information) from or to the Frame Buffer. Each access starts with /SEL = L
followed by a command byte on MOSI. If this byte indicates a frame read or write
access, the next byte (PHR) indicates the frame length followed by the PSDU data, see
Figure 4-7 and Figure 4-8.
On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO
starting with the second byte. After the PSDU data, three more bytes are transferred
containing the link quality indication (LQI) value, the energy detection (ED) value, and
the status information (RX_STATUS) of the received frame. Figure 4-7 illustrates the
packet structure of a Frame Buffer read access. The structure of RX_STATUS is
described in Table 4-3.
AT86RF212
17