AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 131

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

8.2 Frame Transmit Procedure
8168C-MCU Wireless-02/10
A frame transmission comprises of two actions, a Frame Buffer write access and the
transmission of the Frame Buffer content. Both actions can be run in parallel if required
by critical protocol timing.
Figure 8-2 illustrates the frame transmit procedure when writing and transmitting the
frame consecutively. After a Frame Buffer write access, the frame transmission is
initiated by asserting pin 11 (SLP_TR) or writing command TX_START to register 0x02
(TRX_STATE) while the radio transceiver is in state PLL_ON or TX_ARET_ON. The
completion of the transaction is indicated by interrupt IRQ_3 (TRX_END).
Figure 8-2. Transaction between AT86RF212 and Microcontroller during Transmit
Alternatively, a frame transmission can be started first, followed by the Frame Buffer
write access (PSDU data); refer to Figure 8-3. This is applicable for time critical
applications.
Initiating a transmission, either by asserting pin 11 (SLP_TR) or command TX_START
to register bits TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts
transmitting the SHR which is internally generated.
Front end initialization takes one symbol period for PLL settling and PA ramp up. SHR
transmission takes another 40 symbol periods for BPSK or 10 symbol periods for O-
QPSK. The PHR must be available in the Frame Buffer before this time elapses.
Furthermore, the SPI data rate must be higher than the PHY data rate to avoid a Frame
Buffer underrun, which is indicated by IRQ_6 (TRX_UR).
Figure 8-3. Time Optimized Frame Transmit Procedure
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
Write frame data (Frame Buffer access)
Write frame data (Frame Buffer access)
IRQ_3 (TRX_END) issued
IRQ_3 (TRX_END) issued
AT86RF212
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