AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 53

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

AT86RF212
achieve the same functionality as the states RX_AACK_ON and BUSY_RX_AACK with
pin 17 (CLKM) disabled.
The RX_AACK_NOCLK state is entered from RX_AACK_ON by a rising edge at
pin 11 (SLP_TR). The return to RX_AACK_ON state automatically results either from
the reception of a valid frame, indicated by interrupt IRQ_3 (TRX_END), or a falling
edge on pin SLP_TR.
A received frame is considered valid if it passes frame filtering and has a correct FCS. If
an ACK was requested, the radio transceiver enters BUSY_RX_AACK state and follows
the procedure described in section 5.2.3.
After the RX_AACK transaction has been completed, the radio transceiver remains in
RX_AACK_ON state. The AT86RF212 re-enters the RX_AACK_ON_NOCLK state only
by the next rising edge on pin 11 (SLP_TR).
The timing and behavior, when CLKM is disabled or enabled, are described in section
4.6.
Note that RX_AACK_NOCLK is not available for slotted operation mode (see section
5.2.3.5).
5.2.3.5 Slotted Operation – Slotted Acknowledgement
In networks using slotted operation the start of the acknowledgment frame, and thus the
exact timing, must be provided by the microcontroller. Exact timing requirements for the
transmission of acknowledgments in beacon-enabled networks are explained in
IEEE 802.15.4-2006, section 7.5.6.4.2. In conjunction with the microcontroller the
AT86RF212 supports slotted acknowledgement operation. This mode is invoked by
setting register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) to 1.
If an acknowledgment (ACK) frame is to be transmitted in RX_AACK mode, the radio
transceiver expects a rising edge on pin 11 (SLP_TR) to actually start the transmission.
During this waiting period, the transceiver reports SUCCESS_WAIT_FOR_ACK through
register bits TRAC_STATUS (register 0x02, XAH_CTRL_0), see Figure 5-9. The
minimum delay between the occurrence of interrupt IRQ_3 (TRX_END) and pin start of
the ACK frame in slotted operation is 3 symbol periods.
Figure 5-10 illustrates the timing of an RX_AACK transaction in slotted operation. The
acknowledgement frame is ready to transmit 3 symbol times after the reception of the
last symbol of a data or MAC command frame indicated by IRQ_3. The transmission of
the acknowledgement frame is initiated by the microcontroller with the rising edge of pin
11 (SLP_TR) and starts t
later.
TR10
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