AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 52

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

5.2.3.4 RX_AACK_NOCLK – RX_AACK_ON without CLKM
52
AT86RF212
There are two different options for handling reserved frame types.
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
Short Acknowledgment Frame Start Timing
Register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) defines the delay
between the end of the frame reception and the start of the transmission of an
acknowledgment frame.
Table 5-13. ACK Start Timing for Unslotted Operation
Note that this feature can be used in all scenarios, independent of other configurations.
However, shorter acknowledgment timing is especially useful when using High Data
Rate Modes to increase battery lifetime and to improve the overall data throughput,
refer to section 7.1.4.3.
In slotted operation mode, the acknowledgment transmission is actually started by pin
11 (SLP_TR). Table 5-14 shows that the AT86RF212 enables the trigger pin with an
appropriate delay. Thus, a transmission cannot be started earlier.
Table 5-14. ACK Start Timing for Slotted Operation
If the AT86RF212 is listening for an incoming frame and the microcontroller is not
running an application, the microcontroller can be powered down to decrease the total
system power consumption. This special power-down scenario for systems running in
clock synchronous mode (see section 4.2) is supported by the AT86RF212 using the
states RX_AACK_ON_NOCLK and BUSY_RX_AACK_NOCLK, see Figure 5-8. They
Register
Address
Register
Address
Any non-corrupted frame with a reserved frame type is indicated by the interrupt
IRQ_3 (TRX_END). No further frame filtering is applied on those frames. The
interrupt IRQ_5 (AMI) is never generated and no acknowledgment is sent.
Any frame with a reserved frame type is treated like an IEEE 802.15.4 compliant data
frame. This implies the generation of the interrupt IRQ_5 (AMI) upon address
matches. The IRQ_3 (TRX_END) interrupt is only generated if the address matches
and the frame is correct (FCS valid). Then an acknowledgment is sent if the ACK
request subfield of the received frame is set accordingly.
0x17
0x17
Register
Register
Bit
Bit
2
2
Name
AACK_ACK_TIME
Name
AACK_ACK_TIME
Description
0: Standard compliant acknowledgement
delay of 12 symbol periods
1: Reduced acknowledgment delay of 2
symbol periods (BPSK-20, O-QPSK-
{100,200,400}) or 3 symbol periods
(BPSK-40, O-QPSK-{250,500,1000}).
Description
0: Acknowledgment frame transmission
can be triggered after 6 symbol periods.
1: Acknowledgment frame transmission
can be triggered after 3 symbol periods.
8168C-MCU Wireless-02/10