AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 58

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

Figure 5-13. Exemplary Timing of a TX_ARET Transaction (without Pending Data Bit set in ACK Frame)
5.2.5 Interrupt Handling
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AT86RF212
After that, the AT86RF212 switches to receive mode and expects an acknowledgement
response, which is indicated by register subfield TRAC_STATUS (register 0x02,
TRX_STATE) set to SUCCESS_WAIT_FOR_ACK. After a period of aTurnaroundTime
+ aUnitBackoff, the transmission of the ACK frame must have started. During the entire
transaction, including frame transmit, wait for ACK, and ACK receive, the radio
transceiver status register TRX_STATUS (register 0x01, TRX_STATUS) signals
BUSY_TX_ARET.
A successful reception of the acknowledgment frame is indicated by interrupt IRQ_3
(TRX_END). The status register TRX_STATUS (register 0x01, TRX_STATUS) changes
back to TX_ARET_ON. At the same time, register TRAC_STATUS changes to
SUCCESS or to SUCCESS_DATA_PENDING if the “Frame Pending” subfield of the
acknowledgment frame was set to 1.
The interrupt handling in the Extended Operating Mode is similar to the Basic Operating
Mode. Interrupts can be enabled by setting the appropriate bit in register 0x0E
(IRQ_MASK).
For RX_AACK and TX_ARET, the following interrupts inform about the status of a
frame reception and transmission:
• IRQ_2 (RX_START)
• IRQ_3 (TRX_END)
• IRQ_5 (AMI)
For RX_AACK mode, it is recommended to enable only interrupt IRQ_3 (TRX_END).
This interrupt is issued only if the Frame Filter (see section 6.2) reports a matching
address and the FCS is valid (see section 6.3). The usage of other interrupts is
optional.
On reception of a frame, the RX_START interrupt indicates the detection of a correct
synchronization header (SHR) and a non-zero PHY header (PHR). This interrupt is
issued after the PHR. AMI indicates address match, refer to filter rules in section 6.2.
8168C-MCU Wireless-02/10