AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 96

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

• Bit 5 – OQPSK_SCRAM_EN
If set to 1 (reset value), the scrambler is enabled for OQPSK_DATA_RATE = 2 and
BPSK_OQPSK = 1 (O-QPSK is active). Otherwise, the scrambler is disabled.
Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly
required to align different transceivers with OQPSK_SCRAM_EN in order to assure
interoperability.
• Bit 4 – OQPSK_SUB1_RC_EN
The bit is relevant for SUB_MODE = 1 and BPSK_OQPSK = 1.
If set to 0 (reset value), pulse shaping is half-sine filtering for O-QPSK transmission with
1000 kchip/s.
If set to 1, pulse shaping is RC-0.8 filtering. Compared with half-sine filtering, side-lobes
are reduced at the expense of an increased peak to average ratio (~ 1 dB). This mode
is particularly suitable for the Chinese 780 MHz band, refer to IEEE 802.15.4c-2009.
Note that during reception, this bit is not evaluated within the AT86RF212, so it is not
explicitly required to align different transceivers with OQPSK_SUB1_RC_EN in order to
assure interoperability. It is very likely that this also holds for any IEEE 802.15.4-2006
compliant O-QPSK transceiver in the 915 MHz band, since the IEEE 802.15.4-2006
requirements are fulfilled for both types of shaping.
• Bit 3 – BPSK_OQPSK
If set to 0 (reset value), BPSK transmission and reception is applied.
If set to 1, O-QPSK transmission and reception is applied.
Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly
required to align different transceivers with BPSK_OQPSK in order to assure
interoperability.
• Bit 2 – SUB_MODE
If set to 1 (reset value), the chip rate is 1000 kchip/s for BPSK_OQPSK = 1 and 600
kchip/s for BPSK_OQPSK = 0. It permits data rates out of {250, 500, 1000} kbit/s or 40
kbit/s, respectively. This mode is particularly suitable for the 915 MHz band. For O-
QPSK transmission, pulse shaping is either half-sine shaping or RC-0.8 shaping,
depending on OQPSK_SUB1_RC_EN.
If set to 0, the chip rate is 400 kchip/s for BPSK_OQPSK = 1 and 300 kchip/s for
BPSK_OQPSK = 0. It permits data rates out of {100, 200, 400} kbit/s or 20 kbit/s,
respectively. This mode is particularly suitable for the 868.3 MHz band. For O-QPSK
transmission, pulse shaping is always the combination of half-sine shaping and RC-0.2
shaping.
Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly
required to align different transceivers with SUB_MODE in order to assure
interoperability.
• Bit 1:0 – OQPSK_DATA_RATE
These register bits control the O-QPSK data rate during the PSDU part of the frame, as
depicted by Table 7-4. The reset value is OQPSK_DATA_RATE = 0.
Note that during reception, these bits are evaluated within the AT86RF212, so it is
explicitly required to align different transceivers with OQPSK_DATA_RATE in order to
assure interoperability.
AT86RF212
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8168C-MCU Wireless-02/10