AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 73

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

6.2.2 Handling of Reserved Frame Types
6.2.3 Register Description
8168C-MCU Wireless-02/10
Reserved frame types (as described in section 5.2.3.3) are treated according to bits
AACK_UPLD_RES_FT and AACK_FLTR_RES_FT of register 0x17 (XAH_CTRL_1)
with three options:
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
3. AACK_UPLD_RES_FT = 0
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
Table 6-7. Register 0x17 (XAH_CTRL_1)
• Bit 7 – Reserved
• Bit 6 – CSMA_LBT_MODE
Refer to section 6.7.3.
• Bit 5 – AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the
RX_AACK
AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid
FCS. See section 6.2.2 for details.
• Bit 4 – AACK_UPLD_RES_FT
If AACK_UPLD_RES_FT = 1, received frames which are identified as reserved frames
will not be blocked. See section 6.2.2 for details.
• Bit 3 – Reserved
• Bit 2 – AACK_ACK_TIME
Refer to sections 5.2.3.3 and 5.2.6.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Frames of reserved frame type with correct FCS are indicated by the interrupt IRQ_3
(TRX_END). No further frame filtering is applied on these frames. Interrupt IRQ_5
(AMI) is never generated and no acknowledgment is sent.
If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the
RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame. This implies the
generation of the interrupt IRQ_5 (AMI) upon address matches.
Any frame with a reserved frame type is blocked.
Frame
7
Reserved
R/W
0
3
Reserved
R
0
Filter
as
6
CSMA_LBT_MODE
R/W
0
2
AACK_ACK_TIME
R/W
0
an
IEEE
802.15.4
5
AACK_FLTR_RES_FT
R/W
0
1
AACK_PROM_MODE
R/W
0
compliant
AT86RF212
4
AACK_UPLD_RES_FT
R/W
0
0
Reserved
R
0
data
frame.
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If