AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 124

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

7.8.3 PLL Settling Time and Frequency Agility
7.8.4 Calibration Loops
124
AT86RF212
When the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON,
the settling time is typically t
voltage regulator AVREG), including PLL self calibration. For more information, refer to
Table 5-1 and section 7.8.4. The locking of the PLL is indicated with the interrupt IRQ_0
(PLL_LOCK).
Switching between channels within a frequency band in PLL_ON or RX_ON states is
typically done within t
frequency hopping applications.
The PLL frequency in PLL_ON and receive states is 1 MHz below the PLL frequency in
transmit states. When starting the transmit procedure, the PLL frequency is changed to
the transmit frequency within a period of t
transmission. After the transmission, the PLL settles back to the receive frequency
within a period of t
IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK).
Due to variation of temperature, supply voltage, and center frequency, the VCO
characteristics may vary.
To ensure a stable operation, two automated control loops are implemented: center
frequency and delay cell calibration. Both calibration loops are initiated automatically
when the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON.
Additionally, both calibration loops are initiated when the PLL changes to a different
frequency setting.
If the PLL operates for a long time on the same channel or the operating temperature
changes significantly, the calibration loops should be initiated manually. The
recommended calibration interval is 5 minutes or less.
Both calibration loops can be initiated manually by SPI command. To start the
calibration, the device should be in state PLL_ON.
The center frequency calibration can be initiated by setting PLL_CF_START = 1
(register 0x1A, PLL_CF). Center frequency calibration generates (if enabled) a
PLL_UNLOCK interrupt. The calibration loop is completed when the PLL_LOCK
interrupt (if enabled) occurs. The duration of the center frequency calibration loop
depends on the difference between the current CF value and the final CF value. During
the calibration, the CF value is incremented or decremented. Each step takes 8 µs. The
minimum time is 8 µs; the maximum time is 270 µs. The recommended procedure to
start the center frequency calibration is to read the register 0x1A (PLL_CF), to set the
PLL_CF_START register bit to 1, and to write the value back to the register.
The delay cell calibration can be initiated by setting the bit PLL_DCU_START of
register 0x1B (PLL_DCU) to 1. The delay time of the programmable delay unit is
adjusted to the correct value. The calibration works as successive approximation and is
independent of the values in the register 0x1B (PLL_DCU). The duration of the
calibration is t
During both calibration processes, no correct receive or transmit operation is possible.
The recommended state for the calibration is therefore PLL_ON, but calibration is not
blocked at receive or transmit states.
Both calibrations can be executed concurrently.
TR22
= 10 µs.
TR24
TR20
= 32 µs. These frequency changes do not generate the interrupt
= 11 µs. This makes the radio transceiver highly suitable for
TR4
= 200 µs (50 µs plus 150 µs settling time of the analog
TR23
= 16 µs before really starting the
8168C-MCU Wireless-02/10