AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 16

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

4.3 SPI Protocol
Table 4-2. SPI Command Byte Definition
4.3.1 Register Access Mode
16
Bit 7
1
1
0
0
0
0
AT86RF212
Bit 6
0
1
0
1
0
1
Bit 5
1
1
0
0
Bit 4
Referring to Figure 4-2 and Figure 4-3, MOSI is sampled at the rising edge of the SCLK
signal and the output is set at the falling edge of SCLK. The signal must be stable
before and after the rising edge of SCLK as specified by t
parameters 10.4.5 and 10.4.6.
This SPI operational mode is commonly known as “SPI mode 0”.
Each SPI sequence starts with transferring a command byte from the SPI master via
MOSI (see Table 4-2) with MSB first. This command byte defines the SPI access mode
and additional mode-dependent information.
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the
first byte is the PHY_STATUS field, see section 4.4.
In Figure 4-4 to Figure 4-14 and the following sections, logic values stated with XX on
MOSI are ignored by the radio transceiver but need to have a valid logic level. Return
values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first
transferred byte on MOSI is the command byte, including an identifier bit (bit7 = 1), a
read/write select bit (bit 6), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second
byte on MISO (see Figure 4-4).
Figure 4-4. Register Access Mode – Read Access
On write access, the second byte transferred on MOSI contains the write data to the
selected address (see Figure 4-5).
Note:
Register address [5:0]
Register address [5:0]
Bit 3
1. Each SPI access can be configured to return PHY status information
(PHY_STATUS) on MISO, refer to section 4.4.
Reserved
Reserved
Reserved
Reserved
Bit 2
Bit 1
Bit 0
Access Mode
Register access
Frame Buffer access
SRAM access
3
and t
4
; refer to section 10.4,
8168C-MCU Wireless-02/10
Access Type
Read access
Write access
Read access
Write access
Read access
Write access